(Solved) : P1 P2 Imemadd Mux Alu Regs 400ps 100ps 30ps 120ps 200ps 500ps 150ps 100ps 180ps 220ps D Me Q41370471 . . .

P1 | P2 IMemAdd Mux ALU Regs 400ps | 100ps 30ps | 120ps 200ps 500ps 150ps | 100ps 180ps 220ps D-Mem 350ps 1000ps Sign-extend

P1 | P2 IMemAdd Mux ALU Regs 400ps | 100ps 30ps | 120ps 200ps 500ps 150ps | 100ps 180ps 220ps D-Mem 350ps 1000ps Sign-extend 20ps 90ps sll 2 Ops 20ps (a) Which of the two sets of latencies (P1 or P2) seem more reasonable to you? Why? (b) What is the clock cycle time for P1 and P2 if the only type of instructions we need to support are ALU instructions (add, and, etc.)? (c) What is the clock cycle time for P1 and P2 if we only had to support lw instructions? (d) What is the clock cycle time for P1 and P2 if we must support add, beq, lw, and sw instructions? Show transcribed image text P1 | P2 IMemAdd Mux ALU Regs 400ps | 100ps 30ps | 120ps 200ps 500ps 150ps | 100ps 180ps 220ps D-Mem 350ps 1000ps Sign-extend 20ps 90ps sll 2 Ops 20ps (a) Which of the two sets of latencies (P1 or P2) seem more reasonable to you? Why? (b) What is the clock cycle time for P1 and P2 if the only type of instructions we need to support are ALU instructions (add, and, etc.)? (c) What is the clock cycle time for P1 and P2 if we only had to support lw instructions? (d) What is the clock cycle time for P1 and P2 if we must support add, beq, lw, and sw instructions?

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Answer to P1 | P2 IMemAdd Mux ALU Regs 400ps | 100ps 30ps | 120ps 200ps 500ps 150ps | 100ps 180ps 220ps D-Mem 350ps 1000ps Sign-ex…