(Solved) : O Ex Dd Add Result Alu Shift Left 2 Reg2loc Uncondbranch Branch Memread Instruction 31 21 Q41348961 . . .

O EX dd Add result ALU Shift left 2 Reg2Loc Uncondbranch Branch MemRead Instruction (31-21] MemtoReg Control ALUOP MemWrite A4.7.1 [20] <$4.4> Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of

Instruction Opcode Opcode 11-bit opcode range Start Instruction Format Size End 6 191 11 lol lol l 679 713 841 STURB LDURB B.

O EX dd Add result ALU Shift left 2 Reg2Loc Uncondbranch Branch MemRead Instruction (31-21] MemtoReg Control ALUOP MemWrite ALUSrc RegWrite PCR Read address Instruction [9-5) Instruction (20-16) Read register 1 Read 23 Read data 1 register 2 Zero >ALU ALU Instruction [31-0) Instruction memory A ddress data Write Read register data 2 result Instruction (4-0) Write data Registers Write Data data memory Instruction (31-0] O Sign- extend / ALU control Instruction [31-21] 4.7.1 [20] <$4.4> Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in Figure 2.20. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR. Instruction Opcode Opcode 11-bit opcode range Start Instruction Format Size End 6 191 11 lol lol l 679 713 841 STURB LDURB B.cond ORRI EORI STURH LDURH AND ADD ADDI ANDI 10 10 11 11 11 11 10 10 ol lol 1161 1169 1215 BL 1417 1447 1455 lol lol 000101 00111000000 00111000010 01010100 1011001000 1101001000 01111000000 01111000010 10001010000 10001011000 1001000100 1001001000 100101 10101010000 10101011000 1011000100 10110100 10110101 10111000000 10111000100 11001000000 11001000010 11101010000 11001011000 1101000100 110100101 11010011010 11010011011 11010110000 11101010000 11101011000 1111000100 1111001000 111100101 11111000000 11111000010 ORR ADDS ADDIS CBZ CBNZ STURW LDURSW STXR LDXR EOR SUB SUBI MOVZ LSR 160 448 450 672 712 840 960 962 1104 1112 1160 1168 1184 1360 1368 1416 1440 1448 1472 1476 1600 1602 1616 1624 1672 1684 1690 1691 1712 1872 1880 1928 1936 1940 1984 1986 B-format D – format D-format CB – format 1 – format 1 – format D – format D-format R-format R-format 1 – format 1 – format B-format R-format R-format 1 – format CB – format CB – format D – format D-format D-format D – format R-format R-format 1 – format IM – format R-format R-format R-format R-format R-format 1 – format 1 – format IM – format D-format D – format 11 11 11 10 1673 1687 11 LSL 11 BR ANDS SUBS SUBIS ANDIS MOVK STUR LDUR 1929 1937 1943 9 11 11 FIGURE 2.20 LEGv8 instruction encoding. The varying size opcode values can be mapped into the space they occupy in the widest opcodes. By looking at the first 11 bits of the instruction and looking up the value, you can see which instruction it refers to. Show transcribed image text O EX dd Add result ALU Shift left 2 Reg2Loc Uncondbranch Branch MemRead Instruction (31-21] MemtoReg Control ALUOP MemWrite ALUSrc RegWrite PCR Read address Instruction [9-5) Instruction (20-16) Read register 1 Read 23 Read data 1 register 2 Zero >ALU ALU Instruction [31-0) Instruction memory A ddress data Write Read register data 2 result Instruction (4-0) Write data Registers Write Data data memory Instruction (31-0] O Sign- extend / ALU control Instruction [31-21]
4.7.1 [20] Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in Figure 2.20. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR.
Instruction Opcode Opcode 11-bit opcode range Start Instruction Format Size End 6 191 11 lol lol l 679 713 841 STURB LDURB B.cond ORRI EORI STURH LDURH AND ADD ADDI ANDI 10 10 11 11 11 11 10 10 ol lol 1161 1169 1215 BL 1417 1447 1455 lol lol 000101 00111000000 00111000010 01010100 1011001000 1101001000 01111000000 01111000010 10001010000 10001011000 1001000100 1001001000 100101 10101010000 10101011000 1011000100 10110100 10110101 10111000000 10111000100 11001000000 11001000010 11101010000 11001011000 1101000100 110100101 11010011010 11010011011 11010110000 11101010000 11101011000 1111000100 1111001000 111100101 11111000000 11111000010 ORR ADDS ADDIS CBZ CBNZ STURW LDURSW STXR LDXR EOR SUB SUBI MOVZ LSR 160 448 450 672 712 840 960 962 1104 1112 1160 1168 1184 1360 1368 1416 1440 1448 1472 1476 1600 1602 1616 1624 1672 1684 1690 1691 1712 1872 1880 1928 1936 1940 1984 1986 B-format D – format D-format CB – format 1 – format 1 – format D – format D-format R-format R-format 1 – format 1 – format B-format R-format R-format 1 – format CB – format CB – format D – format D-format D-format D – format R-format R-format 1 – format IM – format R-format R-format R-format R-format R-format 1 – format 1 – format IM – format D-format D – format 11 11 11 10 1673 1687 11 LSL 11 BR ANDS SUBS SUBIS ANDIS MOVK STUR LDUR 1929 1937 1943 9 11 11 FIGURE 2.20 LEGv8 instruction encoding. The varying size opcode values can be mapped into the space they occupy in the widest opcodes. By looking at the first 11 bits of the instruction and looking up the value, you can see which instruction it refers to.

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