2) VLiw Consider a 3-wide VLIW pipeline with the following restrictions: Each bundle includes at most 1 control instruction, at most 2 ALU instructions, and at most 2 memory operations. Assume that the same register restrictions as in 1b apply. Assuming that the pipeline has the same stages, forwarding and hazard detection support as in 1 (above), generate a sequence of VLIW bundles from the unrolled code in 2b and schedule them. How do the cycles/iteration compare with 1b? Show transcribed image text
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